1. Technical Field
The present invention relates in general to a method and apparatus to avoid collisions between row activate and column read or column write commands. More particularly, the present invention relates to a method and apparatus for initiating activate commands on “even” command cycles and initiating column commands on “odd” command cycles in order to avoid collisions in a high-speed chip-to-chip memory subsystem.
2. Description of the Related Art
Computer system developers constantly strive to increase a computer system's performance. The developers may focus on optimizing software components and/or hardware components in order to achieve this goal. One hardware optimization approach is to improve a processor's rate of reading from memory and writing to memory.
Hardware developers have designed a dynamic random access memory (DRAM) interface that includes a high-speed chip-to-chip data transfer technology. The interface technology may be implemented on standard CMOS DRAM memory cores and CMOS controller chips for applications such as high-performance main memory, PC graphics, game consoles, advanced digital consumer systems, high-performance networking systems, and other demanding applications requiring high-bandwidth memory subsystems.
The high-speed interface includes a command bus, which is used to send commands between a memory controller and the memory during read operations and write operations. A typical command sequence for either operation would be an “Activate” command, one or more “Column” commands, and a “Precharge” command. The activate command, also referred to as a row command, opens or senses a row or a page. The column command reads to or writes from a column within a row or page. And finally, the precharge command closes a row or a page.
A challenge found with existing art, however, is the possibility of activate commands colliding with column commands. A developer may use a strict time division multiplex (TDM) wheel to manage the timing between the two types of commands. However, this solution may reduce overall performance, which is in contrast to a computer developer's goals.
What is needed, therefore, is a method and apparatus to manage activate commands and column commands in order to avoid collisions with minimal impact on memory subsystem performance.